Harness the power of advanced algorithms and AI to streamline RFIC and MMIC design
Process
Here’s a streamlined, four-step workflow for zapRF, taking you from initial specs to a fabrication-ready GDS-II
Discover
Begin by entering your performance targets and the desired PDK Path.
Define
zapRF proposes ranked circuit architectures based on your specs.
The tool then generates a complete schematic, for bias and impedance review.
Develop
zapRF runs SPICE and fast EM simulations side-by-side to tweak your design until it hits your targets. It then does a full EM check—and if anything shifts, it instantly loops back for another quick optimization.
Deliver
zapRF converts the validated schematic into a correct-by-construction layout, auto-repairing any DRC or LVS violations on the fly.
You then download the GDS-II file and a comprehensive design report ready for tape-out.